Semiconductor devices and methods of fabricating the same

ABSTRACT

A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region.

CROSS REFERENCE TO RELATED APPLICATION

This is a continuation application based on pending application Ser. No.11/709,814, filed Feb. 23, 2007, the entire contents of which is herebyincorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention disclosed herein relates to semiconductor devicesand methods of fabricating the same. More particularly, the inventionrelates to semiconductor devices having a transistor with an extendedchannel width and methods of fabricating the same.

2. Description of the Related Art

As semiconductor memory devices are becoming smaller and/or morehighly-integrated, a channel length and width of transistors includedtherein are becoming smaller. A line-width of an active regioncorresponding to the channel width of the transistor is also beingreduced.

In general, a memory device for storing information may include a cellarray with patterns having minimum line-widths. In a cell array regionof the memory device, an active region and a device isolation region maybe formed such that they have minimum line-widths corresponding to agate pattern of a transistor.

However, as line-width(s) of the gate pattern(s) are reduced, asufficient channel length should be provided in order to suppress and/orprevent short channel effect and leakage current. A structure in whichan effective channel length of the transistor is increased by, e.g.,etching a portion of the active region to form a recess region has beendeveloped. In such cases, the channel length may be secured withoutincreasing a gate line-width by forming the channel of the transistor inthe recess region.

However, in such cases, problems may occur, e.g., the recess region maybe filled with a gate insulating layer, and/or it may be difficult tosecure an effective channel width because the channel is formed in aportion of the recess region. When the effective channel length is notsufficiently secured, a driving current may be decreased and a gatecontrollability of the transistor may be lowered, which may negativelyimpact leakage current and threshold voltage characteristics.

Flash memory devices may employ a method of forming a channel of aselection transistor in a recess region in order to suppress and/orprevent gate-induced drain leakage (GIDL) and punchthrough, and to avoidprogram/erase errors of an outermost cell transistor of a cell string.However, if minimum line-widths are reduced in order to providehighly-integrated devices, e.g., to about or less than about two times athickness of a gate insulating layer, the gate insulating layer maycompletely fill the recess region. Thus, gate controllability of thetransistor may be degraded, which may cause the transistor to operateabnormally.

SUMMARY OF THE INVENTION

The present invention is therefore directed to semiconductor devices andmethods of manufacturing thereof, which substantially overcome one ormore of the problems due to the limitations and disadvantages of therelated art.

It is therefore a feature of an embodiment of the present invention toprovide a semiconductor device that can secure a sufficient effectivechannel width.

It is therefore a separate feature of an embodiment of the presentinvention to provide a method of manufacturing a semiconductor devicethat can secure a sufficient effective channel width.

It is therefore a separate feature of an embodiment of the presentinvention to provide a semiconductor device that can secure an effectivechannel length and an effective channel line-width.

It is therefore a separate feature of an embodiment of the presentinvention to provide a method of manufacturing a semiconductor devicethat can secure a sufficient effective channel width and an effectiveline-width.

At least one of the above another features and advantages of the presentinvention may be realized by providing a semiconductor device includinga device isolation layer disposed in a semiconductor substrate, anactive region defined by the device isolation layer, the active regionincluding a main surface and a recess region including a bottom surfacethat is lower than the main surface, and a gate electrode formed overthe recess region, wherein a top surface of the device isolation layeradjacent to the recess region is lower than the bottom surface of therecess region.

The device isolation layer adjacent to the recess region may be recessedbelow a portion adjacent to the main surface of the active region. Atleast a portion of the active region may protrude higher than the deviceisolation layer. A top surface of the device isolation layer adjacent tothe main surface of the active region may be lower than the main surfaceof the active region. The active region may extend in a row direction,and the active region protrudes higher than the device isolation layerextending adjacent to the active region along the column direction.

At least one of the above another features and advantages of the presentinvention may be separately realized by providing a flash memory deviceincluding a device isolation layer in a semiconductor substrate, anactive region defined by the device isolation layer, the active regionincluding a main surface and a recess region of which a bottom surfaceis lower than the main surface, a word line crossing over the mainsurface of the active region, and a selection gate line disposed inparallel with the word line, and crossing over the recess region,wherein a top surface of the device isolation layer adjacent to therecess region is lower than the bottom surface of the recess region.

The method may further include a pair of recess regions disposed in theactive region, and separated from each other by a predetermineddistance, a ground selection gate line and a string selection gate linecrossing over the respective recess regions, and a plurality of wordlines crossing over the main surface of the active region between theground selection gate line and the string selection gate line. A chargetrapping layer may be interposed between the word line and the activeregion, and between the selection gate line and the active region.

A charge trapping layer may be interposed between the word line and theactive region, and a gate insulating layer may be interposed between theselection gate line and the active region. The device may furtherinclude a tunnel insulating layer, a charge trapping layer and ablocking insulating layer, which may be sequentially stacked between theword line and the active region, wherein the word line disposed over theblocking insulating layer may include a metallic material having a workfunction of about 4.5 eV or greater.

The word line may include a floating gate on the active region, acontrol gate electrode formed on the floating gate, and crossing overthe active region, and an intergate dielectric layer interposed betweenthe floating gate and the control gate electrode, wherein a tunnelinsulating layer may be interposed between the floating gate and theactive region. The selection gate line may include a lower selectiongate, an upper selection gate on the lower selection gate, and anintergate insulating layer interposed between the lower selection gateand the upper selection gate, the gate insulating layer may beinterposed between the lower selection gate and the active region, andthe lower selection gate and the upper selection gate being electricallyconnected to each other.

A width of the selection gate line may be greater than that of therecess region. The selection gate line may cover the active region ateither side of the recess region.

At least one of the above another features and advantages of the presentinvention may be separately realized by providing a method forfabricating a semiconductor device, the method including forming adevice isolation layer in a semiconductor substrate to define an activeregion having a main surface extending in a column direction, forming ahard mask having an opening exposing a portion of the active region,etching a portion of the active region using the hard mask as an etchmask to form a recess region, and etching the device isolation layeradjacent to the recess region such that a top surface of the deviceisolation layer may be lower than a bottom surface of the recess region.The opening may be formed such that it extends in a row direction andexposes the active region and the device isolation layer, and the deviceisolation layer may be etched using the hard mask as an etch mask.

Etching of the device isolation layer may be performed before or afterthe forming of the recess region. The method may further include etchingthe device isolation layer by etch-back process to make the deviceisolation layer lower than the main surface of the active region, andforming the recess region of which a bottom surface is higher than a topsurface of the recessed device isolation layer. Etching of the deviceisolation layer by etch-back process may be performed before or afterthe forming of the recess region. The method may further include forminga word line crossing over the main surface of the active region, and aselection gate line crossing over the recess region.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent to those of ordinary skill in the art bydescribing in detail exemplary embodiments thereof with reference to theattached drawings, in which:

FIGS. 1A and 1B illustrate cross-sectional views of a semiconductordevice according to a first exemplary embodiment of the presentinvention, respectively taken along a first and a second direction thatis perpendicular to the first direction;

FIGS. 2A through 6A illustrate cross-sectional views of stages in amethod of fabricating a semiconductor device according to a firstexemplary embodiment of the present invention, taken along the firstdirection;

FIGS. 2B through 6B illustrate cross-sectional views of stages in amethod of fabricating a semiconductor device according to the firstexemplary embodiment of the present invention, taken along the seconddirection;

FIGS. 7A and 8A illustrate cross-sectional views of stages in a methodof fabricating a semiconductor device according to a second exemplaryembodiment of the present invention, taken along the first direction;and

FIGS. 7B and 8B illustrate cross-sectional views of stages in a methodof fabricating a semiconductor device according to the second exemplaryembodiment of the present invention, taken along the second direction.

DETAILED DESCRIPTION OF THE INVENTION

Korean Patent Application No. 2006-102566, filed on Oct. 20, 2006, inthe Korean Intellectual Property Office, and entitled: “SemiconductorDevice and Method of Fabricating the Same,” is incorporated by referenceherein in its entirety.

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the invention are illustrated. The invention may, however, beembodied in different forms and should not be construed as limited tothe embodiments set forth herein. Rather, these embodiments are providedso that this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art.

In the figures, the dimensions of layers and regions may be exaggeratedfor clarity of illustration. It will also be understood that when alayer or element is referred to as being “on” another layer orsubstrate, it can be directly on the other layer or substrate, orintervening layers may also be present. Further, it will be understoodthat when a layer is referred to as being “under” another layer, it canbe directly under, and one or more intervening layers may also bepresent. In addition, it will also be understood that when a layer isreferred to as being “between” two layers, it can be the only layerbetween the two layers, or one or more intervening layers may also bepresent. Like reference numerals refer to like elements throughout thespecification.

Hereinafter, exemplary embodiments of the invention will be describedwith reference to the accompanying figures.

FIGS. 1A and 1B illustrate cross-sectional views of a semiconductordevice according to a first exemplary embodiment of the presentinvention, respectively taken along a first and a second direction thatis perpendicular to the first direction.

Referring to FIGS. 1A and 1B, a device isolation pattern 52 a may beformed in a semiconductor substrate 50 to define an active region 54. Amain surface region 54 a of the active region 54 defined, e.g., by twoadjacent device isolation patterns 52 a, may extend along the firstdirection, e.g., a column direction, and recess region(s) 60 may beformed in a predetermined region of the active region 54. In a NANDflash memory device, the recess region 60 may correspond to a regionwhere a gate electrode of a selection transistor is formed.

A ground selection line GSL and a string selection line SSL may crossover the active region 54, may extend parallel to each other, and may beseparated from each other by a predetermined distance. A plurality ofword lines WLn may be parallel to and disposed between the groundselection line GSL and the string selection line SSL. The active regions54 under the ground selection line GSL and the string selection line SSLmay correspond to the recess regions 60. The recess regions 60 mayinclude a bottom surface 60 a that may be lower than the main surface 54a of the active region 54. In embodiments of the invention, a width ofthe recess region 60 may be smaller than a width of the string and/orground selection lines SSL and GSL. The string selection line SSL andthe ground selection line GSL may overlap the active region 54 beyondthe recess region 60.

Referring to FIGS. 1A and 1B, an upper surface 52 b of the deviceisolation pattern 52 a disposed adjacent to the recess region 60 may belower than the bottom surface 60 a of the recess region 60. In someembodiments of the invention, the active region 54 may include aprotruding upper portion 54 t that protrudes upward beyond the uppersurface 52 b of the device isolation pattern 52 a. More particularly,e.g., in some embodiments of the invention, when observing across-sectional of the selection transistors taken along a directionparallel to the ground or string selection line GSL or SSL, the mainsurface 54 a of the active region 54, corresponding to the protrudingupper portion 54 t, may have a rounded, sloped or curved shape. Forexample, the protruded upper portion 54 t of the active region 54 mayhave a hemispherical-like, trapezoidal-like, or cone-likecross-sectional shape as a result of etching conditions.

In a charge trap type flash memory device, the word line WLn may includea cell gate electrode 68 and a cell gate insulating layer 62. The cellgate insulating layer 62 may be interposed between the semiconductorsubstrate 50 and the cell gate electrode 68. The cell gate insulatinglayer 62 may be configured with a tunnel insulating layer 62 a, a chargetrapping layer 62 b, and a blocking insulating layer 62 c, which may bestacked in sequence. The ground and string selection lines GSL and SSLmay have the same stack structure as the word line WLn. For example, theground and string selection lines GSL and SSL may include a selectiongate electrode 68 and a selection gate insulating layer interposedbetween the semiconductor substrate 50 and the selection gate electrode68. The selection gate insulating layer may have the same stackstructure as the cell gate insulating layer 62. That is, the selectiongate insulating layer may be configured with a tunnel insulating layer62 a, a charge trapping layer 62 b, and a blocking insulating layer 62c. In other embodiments of the invention, e.g., the selection gateinsulating layer may be configured with a monolayer as a gate insulatinglayer.

A channel region of a memory cell transistor may be formed in the activeregion 54 under the word line WLn. A channel region of the groundselection line GSL may be formed in the active region 54 under theground selection line GSL, and a channel region of the string selectionline SSL may be formed in the active region 54 under the stringselection line SSL. In embodiments of the present invention, the channelregions of the ground and string selection lines GSL and SSL may beformed in the recess regions 60 so that they may have a larger effectivechannel length than the widths of the ground and string selection linesGSL and SSL.

In some embodiments of the invention, because the bottom surface 60 a ofthe recess region 60 may be higher than the upper surface 52 b of thedevice isolation pattern 52 a adjacent thereto, the channel regions ofthe ground and string selection lines GSL and SSL may be formed alongthe protruding upper portion 54 t of the active region 54. Thus, aneffective channel width may be increased, and may be greater than thewidth of the active region 54. The gate insulating layers of the groundand string selection lines GSL and SSL may be formed such that theycover the protruding upper portion 54 t of the active region 54. Moreparticularly, the gate insulating layers of the ground and stringselection lines GSL and SSL may be formed such that they surroundsidewalls of the protruded upper portion 54 t as well as the mainsurface 54 a of the active region can 54. In such embodiments, the mainsurface 54 a and portions of the sidewalls of the protruding upperportion 54 t may be correspond to the channel region.

In conventional devices, when, e.g., the gate insulating layer has athickness of 20 nm, and an active region has a line-width of 40 nm, thegate insulating layer may fill the recess region. Thus, in suchconventional devices, controllability of a gate of the transistor may behindered. In embodiments of the present invention, however, the recessregion 60 may be formed so as to ensure that the recess region 60 maynot be completely filled with the gate insulating layer. Moreparticularly, in some embodiments of the invention, by providing theprotruding upper portion 54 t of the active region 54, respectiveportions of the protruding upper portion 54 t may be used as the channelregion of the transistor.

In embodiments of the present invention, the blocking insulating layer62 c may have a higher dielectric constant than a dielectric constant ofthe tunnel insulating layer 62 a. The cell gate electrode 68 may includea metallic material having a work function greater than about 4.5 eV,wherein the metallic material may be in contact with the blockinginsulating layer 62 c. For example, in some embodiments of theinvention, the cell gate electrode 68 may include a barrier metal layer64, e.g., a tantalum nitride layer, with a metal layer 66 havingexcellent conductivity, e.g., a tungsten and/or a tungsten nitridelayer, formed on the barrier metal layer 64.

FIGS. 2B and 6B illustrate cross-sectional views of stages in a methodof fabricating a semiconductor device according to the first exemplaryembodiment of the present invention, taken along the second direction.

Referring to FIGS. 2A and 2B, a device isolation layer 52 may be formedin a semiconductor substrate 50. The device isolation layer 52 maydefine the active region 54. The device isolation layer 54 may be formedusing a shallow trench isolation (STI) technique.

The main surface 54 a of the active region 54 may extend along the firstdirection, e.g., a column direction. In embodiments of the invention,the active regions 54 may be disposed to extend along the firstdirection, i.e., substantially perpendicular to the first directionalong which the gate and/or string selection lines GSL, SSL may extend.

Referring to FIGS. 3A and 3B, a hard mask 56 may be formed on theresultant structure. The hard mask 56 may have an opening 58 exposing aportion of the active region 54. The opening 58 may extend in the seconddirection intersecting the active regions 54 and may expose the deviceisolation layer 52 defining the active regions 54 as well as the activeregions 54.

In some embodiments of the invention, the opening 58 may be placed overa region where a channel of the selection transistor will be formed inthe NAND type cell array, and may have a smaller width W1 than that ofthe gate line of the select transistor.

Referring to FIGS. 4A and 4B, the active region 54 may be etched to formthe recess region 60 using the hard mask 56 as an etch mask. The bottomsurface 60 a of the recess region 60 may be positioned lower than themain surface 54 a of the active region. Therefore, the device isolationlayer 52 adjacent to the recess region 60 may include a protrusion 52 tthat may be higher than the bottom surface 60 a of the recess region 60.

Referring to FIGS. 5A and 5B, the device isolation layer 52 may then beetched using the hard mask 56 as an etch mask. In some embodiments ofthe invention, the hard mask 56 may be etched using a different etchingsolution than that used to etch the active region 54. Thus, theprotrusions 52 t of the device isolation layer 52 adjacent to the recessregion 60 may be etched such the device isolation pattern 52 b may beformed. More particularly, the upper surface 52 a of the deviceisolation pattern 52 a may be lower than the bottom surface 60 a of therecess region 60. Thus, the active region 54 may include protruded upperportion(s) 54 t, which may be higher than the upper surface 52 b of thedevice isolation pattern 52 a. The protruded upper portion 54 t of theactive region 54 may have a hemispherical-like, trapezoidal-like, orcone-like cross-sectional shape as a result of the etching conditions.

Thus, because the active region 54 may include the recess region 60having the bottom surface 60 a that may be lower than the main surface54 a of the active region 54, and the device isolation pattern 52 aadjacent to the recess region 60 may be lower than the bottom surface 60a of the recess region 60, sidewalls of the active region 54 may beexposed at a region higher than the device isolation pattern 52 s. Moreparticularly, sidewalls of the active region 54 may be exposed at aregion higher than the upper surface 52 a of the device isolationpattern 52 b.

In embodiments of the invention, the device isolation layer 52 may beetched using the hard mask 56 as an etch mask and thus, only the deviceisolation layer 52 adjacent to the recess region 60 may be etched, i.e.,shortened to become lower than the active region 54.

Alternatively, the device isolation layer 52 may be etched over anentire surface of the cell array region by an etch-back process afterremoving the hard mask layer 56, whereby the device isolation layer 52adjacent to the main surface of the active region 54 may be lower thanthe active region 54. In such cases, because the device isolation layer52 may be etched to be lower than the bottom surface 60 a of the recessregion 60, the upper surface 52 b of the device isolation pattern 52 aadjacent to the recess region 60 may be lower than the bottom surface 60a of the recess region 60.

Alternatively, it is possible to provide the device isolation layer 52at a level lower than the recess region 60 by etching the deviceisolation layer 52 before forming the recess region 60. That is, afteretching the device isolation layer 52 using the hard mask 56 as an etchmask, the active region 54 may be etched using the hard mask 56 as anetch mask. Before forming the hard mask 56, the device isolation layer52 may be etched in the cell array so that the upper surface 52 b of thedevice isolation layer 52 becomes lower than the main surface 54 a ofthe active region 54. Thereafter, the hard mask 56 may be formed, andthe recess region 60 may then be formed using the hard mask 56.

When the top surface of the device isolation layer 52 is lower than themain surface of the active region 54, the active region 54 may have aprotrusion that is higher than the device isolation layer 52. That is,the active region 54 may have a sidewall or portion extending from themain surface 54 a thereof that is higher than, i.e., protruding,relative to the upper surface 52 b of the device isolation pattern 52 a.As a result, the channel width of the cell transistor can be increasedbecause the channel of the cell transistor can be formed on the mainsurface 54 a and/or protruding sidewall of the active region 54.

Referring to FIGS. 6A and 6B, the hard mask 56 may be removed and thegate insulating layer 62 may then formed on a surface, e.g., an entiresurface, of the active region 54. In charge trap type flash memorydevices, the gate insulating layer 62 may have a multi-stacked structureincluding a charge trapping layer. For example, the gate insulatinglayer 62 may include the tunnel insulating layer 62 a, the chargetrapping layer 62 b and the blocking insulating layer 62 c.

The gate electrode layer 68 may then be formed on the gate insulatinglayer 62. The gate electrode layer 68 may include the barrier metallayer 64 formed of a metallic material having a work function of about4.5 eV or greater. For example, the barrier metal layer 64 may includetantalum nitride.

The metal layer 66 with excellent conductivity may then be formed on thebarrier metal layer 64. The metal layer 66 may be formed of tungstenand/or tungsten nitride layer. Subsequently, as shown in FIGS. 1A and1B, at least the gate electrode layer 68 may be patterned to form aplurality of word lines WLn crossing over the active region 54, andground and string section lines GSL and SSL crossing over the recessregion 60.

More particularly with regard to the gate insulating layer 62, inembodiments of the invention, the gate insulating layer 62 may beconformally formed along a surface profile of the recess region 60. Inconventional devices, when the minimum width is reduced so that thewidth of the active region 54 is two times or less the thickness of thegate insulating layer 62, the recess region 60 was filled with the gateinsulating layer.

In embodiments of the present invention, however, because the recessregion 60 may include the bottom surface 60 a that is higher than theupper surface 52 b of the device isolation pattern 52 a, the recessregion 60 may not be filled with the gate insulating layer 62. Thus,embodiments of the invention may be advantageous over conventionaldevices at least because embodiments of the invention provide the activeregion 54 and the recess region 60 such that the recess region 60 maynot be completely filled with a gate insulating layer formed thereon.Rather, in embodiments of the invention, the gate insulating layer 62may be formed so as to encompass the bottom surface 60 a of the recessregion 60, and thus a contact area between the active region 54 and thegate insulating layer 62 may be enlarged. Therefore, it is possible toincrease the channel width of the selection transistor defined in theactive region under the ground and string selection lines GSL and SSL.

In the above description of exemplary embodiments, the gate insulatinglayer 62 is illustrated as having a multi-stacked structure all over theactive region. However, embodiments of the invention are not limited tosuch a structure. For example, the gate insulating layer 62 may have amulti-stacked structure in a region where the word lines are formed, butmay have a monolayer structure in a region where the ground and stringselection lines GSL and SSL are formed. In such embodiments, afterforming a multi-layered gate insulating layer 62, the multi-layered gateinsulating layer 62 may be partially removed to form a monolayered gateinsulating layer.

FIGS. 7A and 8A illustrate cross-sectional views of stages in a methodof fabricating a semiconductor device according to a second exemplaryembodiment of the present invention, taken along the first direction.FIGS. 7B and 8B illustrate cross-sectional views of stages in a methodof fabricating a semiconductor device according to the second exemplaryembodiment of the present invention, taken along the second direction.

Referring to FIGS. 7A and 7B, a floating gate type flash memory devicemay include a floating gate. In the following description, in general,only differences between the first exemplary embodiment described aboveand the second exemplary embodiment illustrated in FIGS. 7A through 8Bwill be described. Similar to the exemplary process described above withreference to FIGS. 5A and 5B, the recess region 60 may be formed in theactive region 54, and at least the device isolation pattern 52 aadjacent to the recess region 60 may be etched to have a top surfacethereof lower than the bottom surface 60 a of the recess region 60.

Afterwards, a gate insulating layer 162 may be formed on the activeregion 54, and a floating gate layer 164, an intergate dielectric layer166, and a control gate electrode layer 168 may be formed on the gateinsulating layer 162. In some embodiments of the invention, theintergate dielectric layer 166 may be formed such that it has an openingOX over the recess region 60, so that the floating gate layer 164 andthe control gate electrode layer 168 may be connected to each other.

The gate insulating layer 162 may be a thin tunnel insulating layer at aportion where the cell transistor will be formed, whereas it may bethicker than the tunnel insulating layer at a portion where theselection transistor will be formed.

Referring to FIGS. 8A and 8B, the control gate electrode layer 168, theintergate dielectric layer 166 and the floating gate layer 164 may besequentially patterned to form word lines WLn crossing over the activeregion 54 and the ground and selection lines GSL and SSL crossing overthe recess region 60.

The word line WLn may have a multi-stacked structure in which thefloating gate layer 164, the intergate dielectric layer 166 and thecontrol gate layer 168 are stacked over the tunnel insulating layer 162in sequence. Each of the ground and string selection lines GSL and SSLmay include a lower selection gate corresponding to the floating gate164, an intergate insulating layer corresponding to the intergatedielectric layer 166, and an upper selection gate corresponding to thecontrol gate electrode 168.

Embodiments of the present invention enable an effective channel widthas well as an effective channel length of a transistor, including achannel formed in the recess region, to be secured. When one or moreaspects of the present invention is applied to the flash memory device,it is possible to provide a selection transistor having a largereffective channel length than a gate linewidth. In addition, even if theminimum linewidth is reduced, embodiments of the invention enablesuppression and/or prevention of degradation of gate controllability forthe channel while securing the effective channel width as well.

Furthermore, when forming an active region where a cell transistor willbe formed such that it protrudes higher than a device isolation layer, achannel width of the cell transistor can be increased.

Exemplary embodiments of the present invention have been disclosedherein, and although specific terms are employed, they are used and areto be interpreted in a generic and descriptive sense only and not forpurpose of limitation. Accordingly, it will be understood by those ofordinary skill in the art that various changes in form and details maybe made without departing from the spirit and scope of the presentinvention as set forth in the following claims.

1-20. (canceled)
 21. A flash memory device, comprising: an active region including a main surface and a pair of recess regions of which a bottom surface is lower than the main surface, the pair of recess regions disposed in the active region, and separated from each other by a predetermined distance; a ground selection gate line and a string selection gate line crossing over the respective recess regions; and at the least one of a word line crossing over the main surface of the active region between the ground selection gate line and the string selection gate line.
 22. The flash memory device as claimed in claim 21, wherein a charge trapping layer is interposed between the word line and the active region, and between the active region and a selection gate line including the ground selection gate line and the string selection gate line.
 23. The flash memory device as claimed in claim 21, wherein a charge trapping layer is interposed between the word line and the active region, and a gate insulating layer is interposed between the active region and a selection gate line including the ground selection gate line and the string selection gate line.
 24. The flash memory device as claimed in claim 21, further comprising a tunnel insulating layer, a charge trapping layer and a blocking insulating layer, which are sequentially stacked between the word line and the active region, wherein the word line disposed over the blocking insulating layer includes a metallic material having a work function of about 4.5 eV or greater.
 25. The flash memory device as claimed in claim 21, wherein the word line comprises: a floating gate on the active region; a control gate electrode formed on the floating gate, and crossing over the active region; and an intergate dielectric layer interposed between the floating gate and the control gate electrode, wherein a tunnel insulating layer is interposed between the floating gate and the active region.
 26. The flash memory device as claimed in claim 21, wherein the ground selection gate line and the string selection gate line comprise: a lower selection gate; an upper selection gate on the lower selection gate; and an intergate insulating layer interposed between the lower selection gate and the upper selection gate, the gate insulating layer being interposed between the lower selection gate and the active region, and the lower selection gate and the upper selection gate being electrically connected to each other.
 27. The flash memory device as claimed in claim 21, wherein widths of the ground selection and the string selection gate line are greater than that of the recess regions.
 28. The flash memory device as claimed in claim 27, wherein the ground selection gate line and the string selection gate line cover the active region at either side of the respective pair of recess regions. 